1. general description the 74ahc594-q100; 74ahct594-q100 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (lsttl). it is specified in compliance with jedec standard no. 7a. the 74ahc594-q100; 74ahct594-q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit d-type storage register. separate clocks (shcp and stcp) and direct overriding clears (shr and str ) are provided on both the shift and storage registers. a serial output (q7s) is provided for cascading purposes. both the shift and storage register clocks are po sitive-edge triggered. if the user wishes to connect both clocks together, the shift register is always one count pulse ahead of the storage register. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have schmitt trigger actions ? inputs accept voltages higher than v cc ? wide supply voltage range from 2.0 v to 5.5 v ? 8-bit serial-in, parallel-out shift register with storage ? independent direct overriding clea rs on shift and storage registers ? independent clocks for shift and storage registers ? latch-up performance exceeds 100 ma per jesd78 class ii ? input levels: ? for 74ahc594-q100: cmos level ? for 74ahct594-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74ahc594-q100; 74ahct594-q100 8-bit shift register with output register rev. 2 ? 4 july 2013 product data sheet
74ahc_ahct594_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 2 ? 4 july 2013 2 of 24 nxp semiconductors 74ahc594-q100; 74ahct594-q100 8-bit shift register with output register 3. applications ? serial-to parallel data conversion ? remote control holding register 4. ordering information table 1. ordering information type number package temperature range name description version 74ahc594-q100 74ahc594d-q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74ahc594db-q100 ? 40 ? c to +125 ? c ssop16 plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 74ahc594pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74AHC594BQ-Q100 ? 40 ? c to +125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1 74ahct594-q100 74ahct594d-q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74ahct594db-q100 ? 40 ? c to +125 ? c ssop16 plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 74ahct594pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74ahct594bq-q100 ? 40 ? c to +125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1
74ahc_ahct594_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 2 ? 4 july 2013 3 of 24 nxp semiconductors 74ahc594-q100; 74ahct594-q100 8-bit shift register with output register 5. functional diagram fig 1. functional diagram mbc320 q7 q0 q1 q2 q3 q4 q5 q6 ds shcp shr stcp str 14 10 13 11 12 15 9 1234567 8-stage shift register 8-bit storage register q7s fig 2. logic symbol fig 3. iec logic symbol mbc319 stcp shcp str shr ds q7s q0 q1 q2 q3 q4 q5 q6 q7 14 10 13 11 12 15 9 1 2 3 4 5 6 7 mbc322 shcp stcp q0 q1 q2 q3 q4 q5 q6 q7 shr str ds 15 9 1 2 3 4 5 6 7 1d 2d c1/ 10 11 14 c2 12 13 r2 srg8r1 q7s
74ahc_ahct594_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 2 ? 4 july 2013 4 of 24 nxp semiconductors 74ahc594-q100; 74ahct594-q100 8-bit shift register with output register 6. pinning information 6.1 pinning fig 4. logic diagram mbc321 q0 q1 q2 q3 q4 q5 q6 ds shcp shr stcp str d q cp ffsh 0 r stage 0 d q cp ffst 0 r stages 1 to 6 dq q7 dq cp ffsh 7 r stage 7 d q cp ffst 7 r q7s fig 5. pin configuration so16 4 9 & & 4 4 4 ' 6 4 6 7 5 4 6 7 & |